As the semiconductor industry introduces new generations of integrated circuits (IC) having higher performance and more functionality, the density of the elements forming the ICs increases, while the dimensions, sizes, and spacing between components or elements are reduced. In the past, such reductions were limited only by the ability to define the structures photo-lithographically, and device geometries having smaller dimensions create new limiting factors. For example, for any two adjacent conductive features, as the distance between the conductive features decreases, the resulting capacitance (a function of the dielectric constant (k value) of the insulating material divided by the distance between the conductive features) increases. This increased capacitance results in increased power consumption and increased resistive-capacitive (RC) delay. Therefore, the continual improvement in semiconductor IC performance and functionality is dependent upon developing materials with low k values.
Since the material with the lowest dielectric constant is air or vacuum (k=1.0), low-k dielectric materials typically comprise porous materials. Furthermore, air-gaps are formed to further reduce effective k values.
FIGS. 1A through 1C illustrate a conventional process for forming an interconnect structure with air-gaps. Referring to FIG. 1A, copper lines 4 and corresponding diffusion barrier layers 5 are formed in inter-metal dielectric 6, which has a low k value, and contains a high concentration of carbon. During the formation of copper lines 4, portions 8 of inter-metal dielectric 6, which were exposed during the formation of copper lines 4, are damaged, and hence have a low concentration of carbon. The damaged low-k dielectric portions 8 have a high k value, which may be as high as about 7, causing a significant increase in the overall parasitic capacitance. The damaged portions 8 are etched to form air-gaps 10, as illustrated in FIG. 1B. Subsequently, as shown in FIG. 1C, etch stop layer (ESL) 12 is formed, followed by the formation of the metal lines 19 and vias 18.
Although the formation of air-gaps 10 reduces the parasitic capacitance of the interconnect structure, the conventional process suffers from drawbacks. When ESL 12 is formed, due to the exposure of air-gaps 10, ESL 12 will be filled into air-gaps 10. Typically, ESL 12 is formed of materials having a greater dielectric constant than that of low-k dielectric 6. As a result, the line capacitances between copper lines 4 are increased. Experiment results have revealed that the formation of air-gaps 10 results in the line capacitances to be reduced by about 14 percent. However, after the formation of ESL 12, the line capacitances are only about 4.0 percent lower than the line capacitances before air-gaps 10 are formed. The benefit of having air-gaps is thus significantly compromised.
A further problem is that air-gaps 10 may cause diffusion barrier layer 16 to be discontinuous. When a misalignment occurs and vias 18 land over air-gaps 10, the corresponding portions of diffusion barrier layer 16 also land over air-gaps 10. As a result, copper will fall into air-gaps 10 during the formation of vias 18, and may diffuse into air-gaps 10 even after the formation of vias 18. In turn, copper may diffuse into inter-metal dielectric 6, causing the degradation of the integrated circuit. This also means that the misalignment window for forming vias 18 is significantly reduced.
Accordingly, what is needed in the art is an interconnect structure that may incorporate steps for removing damaged low-k dielectric layers thereof to take advantage of the benefits associated with reduced parasitic capacitances while at the same time overcoming the deficiencies of the prior art.